http://www.timebie.com/timezone/southafricanevada.php Web28 ago 2016 · In SystemVerilog assertion there are two expressions. a ##0 b a -> b Actually, it looks like a similar in expressions. First of this expression is checking a is asserted (1) and after 0 clock cycle b is asserted (1) or not. Second expression is checking b is (on)asserted when a is asserted (1) then on same posedge b is asserted (1) or not.

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